Parallel Level-Set Based Approach for Etching Topography Simulation
Published in International Conference on ASIC, 2025
This paper introduces a parallel level set method framework for simulating etching topography in semiconductor manufacturing. The approach leverages high-order numerical schemes and OpenMP-based parallelization to achieve efficient and accurate simulations of complex etching processes.
Abstract
Semiconductor etching simulation is crucial for predicting and optimizing manufacturing processes. This work presents a parallel 3D Level Set Method (LSM) framework for etching simulation featuring high-order spatial and temporal discretization, multi-threaded parallelization using OpenMP, robust handling of orientation-dependent etching, and validation against industrial standards. The implementation achieves super linear speedup and demonstrates high accuracy in capturing topological changes during etching processes.
Key Contributions
- Implementation of high-order numerical schemes for improved accuracy in etching simulations
- Development of an efficient parallelization strategy using OpenMP
- Comprehensive validation using quantitative metrics against industrial standards
- Demonstration of super linear speedup in parallel execution