Parallel Level-Set Based Approach for Etching Topography Simulation

Abstract

This talk presents a parallel Level Set Method (LSM) framework for simulating material interface evolution during semiconductor etching. The LSM naturally handles sharp corners, topological changes (merging and splitting), and large speed variations by solving Hamilton-Jacobi equations on structured grids. Key features include multiple high-order time integration and spatial reconstruction schemes, surface extraction, material-dependent etching, and parallel computation via OpenMP combined with sparse matrix operations. The implementation achieves super linear speedup. Validation using comprehensive quantitative metrics confirms high accuracy and strong robustness in capturing topological changes. Benchmarks demonstrate high similarity with industrial standards.

Introduction

Semiconductor etching is a critical manufacturing process for creating intricate microstructures through selective material removal. Accurate simulation of this process is essential to reduce development costs. The process involves tracking evolving interfaces with complex geometries, multi-material interactions, and challenging boundary conditions. Traditional methods face limitations: marker/string techniques suffer from swallowtail instabilities during topological changes; cell-based approaches compromise geometric accuracy; and characteristic methods exhibit 3D stability issues. The Level Set Method (LSM), pioneered by Osher and Sethian, overcomes these challenges by implicitly representing interfaces as zero-level sets of higher-dimensional functions. This approach naturally handles topological changes, sharp corners, and extreme velocity variations while providing entropy-satisfying weak solutions to Hamilton-Jacobi equations.

This work introduces a parallel 3D LSM framework for etching simulation featuring:

1. High-order spatial and temporal discretization for improved accuracy
2. Multi-threaded parallelization using OpenMP for enhanced computational efficiency
3. Robust handling of orientation-dependent etching and multi-material interactions
4. Validation against industrial standards with quantitative metrics verifying accurate topology management

Methodology

Level Set Formulation

The level set method represents the evolving etching front Γ(t) as the zero level set of a signed distance function φ(x, t):

This implicit representation naturally handles topological changes (splitting/merging) and complex geometries.

The evolution of φ is governed by the Hamilton-Jacobi equation:

For semiconductor applications, the velocity field U depends on the material:

where $R_m$ is the vertical etching rate of material $m$, and $\alpha < 1$ controls lateral etching.

Spatial Discretization

We employ high-order finite volume schemes with specialized discretization for the hyperbolic convective term $\mathbf{U} \cdot \nabla \phi$:

1. First-Order Upwind: A monotonic but diffusive scheme
2. Roe’s Scheme with MUSCL: Combines the Roe solver with piecewise linear reconstruction
3. Roe’s Scheme with QUICK Interpolation: Utilizes third-order accuracy in smooth regions

Time Integration

Three schemes are implemented for temporal discretization:

1. Backward Euler: 1st-order, unconditionally stable
2. Crank-Nicolson: 2nd-order, unconditionally stable
3. TVD Runge-Kutta 3: 3rd-order, explicit with TVD properties

Parallel Implementation

To manage the computational demands of 3D semiconductor etching simulations, we adopt a high-performance computing technique that combines sparse linear algebra optimization with advanced solver configuration:

• Triplet storage with thread-local buffers
• Pre-computation of sparsity patterns to eliminate dynamic allocation
• Lock-free insertion using OpenMP parallel
• Compressed Row Storage (CRS) with blocked layouts for cache locality
• SIMD-optimized packing for arithmetic throughput
• Accelerated BiCGSTAB solver with diagonal preconditioning
• OpenMP parallelization of stencil operations

Results

Simulation performed on 600 × 600 × 600 grid ($\Delta t = 1s$). Results at $t = 60s$ compared against SEMulator3D. Hardware: Linux server with Intel® Xeon® Gold 6230R CPU @ 2.10 GHz.

Performance Comparison

Third-order Runge-Kutta scales significantly better, achieving 11.22× speedup at 16 threads. Backward Euler shows scaling limitations beyond 8 threads.

Geometric Accuracy

Conclusion

This work presents a high-fidelity, parallel level-set framework for simulating semiconductor etching processes with complex topographies. By integrating high-order spatial reconstruction and time integration schemes, the implementation achieves both numerical stability and geometric accuracy. The method effectively captures sharp corners, topological transitions, and anisotropic etching behaviors, overcoming key limitations of traditional front-tracking approaches.

The adoption of OpenMP-parallelized sparse matrix solvers and stencil operations enables efficient large-scale 3D simulations. Benchmark results show that the third-order Runge-Kutta scheme not only improves accuracy but also demonstrates superior parallel scalability—achieving up to 11.22× speedup with 16 threads. Validation against industrial standards confirms that the proposed method maintains a high degree of geometric similarity with commercial tools.

Altogether, the proposed framework offers a robust, extensible, and computationally efficient platform for simulating etching topographies.